-- Basic components for LOVE #INCLUDE "love.inc" #INCLUDE "trace.inc" #USE "plumbing" #USE "widgets" #USE "lib" PROC id.component (PROC.CTL? ctl) PROC id (CHAN CHUNK in?, out!) WHILE TRUE CHUNK ch: SEQ in ? ch out ! ch : STREAM.WIRE? inw: STREAM.WIRE! inw.c: PORT.CTL? outp: PORT.CTL! outp.c: SEQ ctl[resp] ! reg.counts; 1; 1 inw, inw.c := MOBILE STREAM.WIRE ctl[resp] ! reg.stream.in; inw.c outp, outp.c := MOBILE PORT.CTL ctl[resp] ! reg.stream.out; outp.c ctl[resp] ! reg.done CHAN CHUNK thru: PAR id (inw[c]?, thru!) stream.port (thru?, outp) : PROC plus.component (PROC.CTL? ctl) PROC plus (CHAN CHUNK in.a?, in.b?, out!) WHILE TRUE CHUNK a, b: SEQ PAR in.a ? a in.b ? b SEQ i = 0 FOR CHUNK.SIZE a[i] := a[i] + b[i] out ! a : INITIAL MOBILE []STREAM.WIRE? ins IS MOBILE [2]STREAM.WIRE?: CHAN CHUNK a, b: PORT.CTL? outp: PORT.CTL! outp.c: SEQ ctl[resp] ! reg.counts; 2; 1 SEQ i = 0 FOR 2 STREAM.WIRE! c: SEQ ins[i], c := MOBILE STREAM.WIRE ctl[resp] ! reg.stream.in; c outp, outp.c := MOBILE PORT.CTL ctl[resp] ! reg.stream.out; outp.c ctl[resp] ! reg.done CHAN CHUNK thru: PAR sync.inputs (ins, [a!, b!]) plus (a?, b?, thru!) stream.port (thru?, outp) : PROC times.component (PROC.CTL? ctl) PROC times (CHAN CHUNK in.a?, in.b?, out!) WHILE TRUE CHUNK a, b: SEQ PAR in.a ? a in.b ? b SEQ i = 0 FOR CHUNK.SIZE a[i] := a[i] * b[i] out ! a : INITIAL MOBILE []STREAM.WIRE? ins IS MOBILE [2]STREAM.WIRE?: CHAN CHUNK a, b: PORT.CTL? outp: PORT.CTL! outp.c: SEQ ctl[resp] ! reg.counts; 2; 1 SEQ i = 0 FOR 2 STREAM.WIRE! c: SEQ ins[i], c := MOBILE STREAM.WIRE ctl[resp] ! reg.stream.in; c outp, outp.c := MOBILE PORT.CTL ctl[resp] ! reg.stream.out; outp.c ctl[resp] ! reg.done CHAN CHUNK thru: PAR sync.inputs (ins, [a!, b!]) times (a?, b?, thru!) stream.port (thru?, outp) : PROC const.component (PROC.CTL? ctl) PROC const (CHAN REAL32 in?, CHAN CHUNK out!) INITIAL REAL32 value IS 440.0: INITIAL REAL32 prev.value IS value: WHILE TRUE CHUNK ch: SEQ PRI ALT in ? value SKIP TRUE & SKIP SKIP make.chunk (ch) IF value = prev.value ch := [i = 0 FOR CHUNK.SIZE | value] TRUE SEQ SEQ i = 0 FOR CHUNK.SIZE VAL REAL32 v IS (REAL32 ROUND i) / (REAL32 ROUND CHUNK.SIZE): ch[i] := ((1.0 - v) * prev.value) + (v * value) prev.value := value out ! ch : PORT.CTL? outp: PORT.CTL! outp.c: PROC.UI? ui: PROC.UI! ui.c: SEQ ctl[resp] ! reg.counts; 0; 1 outp, outp.c := MOBILE PORT.CTL ctl[resp] ! reg.stream.out; outp.c ui, ui.c := MOBILE PROC.UI ctl[resp] ! reg.ui; ui.c ctl[resp] ! reg.done CHAN REAL32 value, value.b: CHAN CHUNK thru: CHAN VEC.EVENT e0: CHAN MOBILE []VEC.ENTRY g0: PAR value.widget (ui[event]?, e0!, g0?, ui[disp]!, 0.1, 0.1, 0.8, 0.8, 440.0, value!) overwriting.buf.real32 (value?, value.b!) dump.events (e0?) const (value.b?, thru!) stream.port (thru?, outp) : PROC scale.component (PROC.CTL? ctl) PROC scale (CHAN REAL32 times.in?, plus.in?, CHAN CHUNK in?, out!) INITIAL REAL32 times IS 1.0: INITIAL REAL32 plus IS 0.0: WHILE TRUE PRI ALT times.in ? times SKIP plus.in ? plus SKIP CHUNK ch: in ? ch SEQ SEQ i = 0 FOR SIZE ch ch[i] := (ch[i] * times) + plus out ! ch : STREAM.WIRE? inw: STREAM.WIRE! inw.c: PORT.CTL? outp: PORT.CTL! outp.c: PROC.UI? ui: PROC.UI! ui.c: SEQ ctl[resp] ! reg.counts; 1; 1 inw, inw.c := MOBILE STREAM.WIRE ctl[resp] ! reg.stream.in; inw.c outp, outp.c := MOBILE PORT.CTL ctl[resp] ! reg.stream.out; outp.c ui, ui.c := MOBILE PROC.UI ctl[resp] ! reg.ui; ui.c ctl[resp] ! reg.done CHAN REAL32 times, plus, times.b, plus.b: CHAN CHUNK thru: CHAN VEC.EVENT e0, e1: CHAN MOBILE []VEC.ENTRY g0, g1: PAR value.widget (ui[event]?, e0!, g0?, g1!, 0.1, 0.1, 0.8, 0.4, 1.0, times!) overwriting.buf.real32 (times?, times.b!) value.widget (e0?, e1!, g1?, ui[disp]!, 0.1, 0.5, 0.8, 0.4, 0.0, plus!) overwriting.buf.real32 (plus?, plus.b!) dump.events (e1?) scale (times.b?, plus.b?, inw[c]?, thru!) stream.port (thru?, outp) :